C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 22.2. PCA0MD: PCA0 Mode
SFR Page:
all pages
SFR Address: 0xD9
R/W
R/W
R/W
WDLCK
Bit5
R/W
–
R/W
CPS2
Bit3
R/W
CPS1
Bit2
R/W
CPS0
Bit1
R/W
ECF
Bit0
Reset Value
CIDL
Bit7
WDTE
Bit6
01000000
Bit4
Bit 7:
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 5 is used as the watchdog timer.
0: Watchdog Timer disabled.
Bit 6:
Bit 5:
1: PCA Module 5 enabled as Watchdog Timer.
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Bit 4:
UNUSED. Read = 0b, Write = don't care.
Bits 3–1: CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
CPS2 CPS1 CPS0
Timebase
0
0
0
0
0
1
0
1
0
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
System clock
External clock divided by 8 (synchronized with system clock)
Reserved
Reserved
Note: External clock divided by 8 is synchronized with the system clock.
Bit 0:
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Note:When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the contents of the
PCA0MD register, the Watchdog Timer must first be disabled.
Rev. 1.0
277
SILICON [ SILICON ]
