C8051F360/1/2/3/4/5/6/7/8/9
22.4. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of PCA0.
SFR Definition 22.1. PCA0CN: PCA Control
SFR Page:
SFR Address: 0xD8
all pages
(bit addressable)
R/W
R/W
CR
Bit6
R/W
CCF5
Bit5
R/W
CCF4
Bit4
R/W
CCF3
Bit3
R/W
CCF2
Bit2
R/W
CCF1
Bit1
R/W
CCF0
Bit0
Reset Value
CF
Bit7
00000000
Bit 7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vec-
tor to the CF interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
CCF5: PCA0 Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is
enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
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Rev. 1.0
SILICON [ SILICON ]
