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Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 22.4, where PCA0L is the value of the PCA0L register
at the time of the update.
Equation 22.4. Watchdog Timer Offset in PCA Clocks
Offset = (256 × PCA0CPL5) + (256 – PCA0L)
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
22.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
•
•
•
•
Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
Load PCA0CPL5 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
•
•
Enable the WDT by setting the WDTE bit to ‘1’.
Write a value to PCA0CPH5 to reload the WDT.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 22.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 22.3 lists some example timeout intervals for typical
system clocks.
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