C8051F360/1/2/3/4/5/6/7/8/9
To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external
clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.
Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and PLL-
PWR bits can be cleared at the same time.
SFR Definition 16.6. PLL0CN: PLL Control
SFR Page:
F
SFR Address: 0xB3
R/W
R/W
–
R/W
–
R
R/W
R/W
R/W
R/W
Reset Value
–
PLLLCK Reserved PLLSRC PLLEN PLLPWR 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bit 4:
PLLLCK: PLL Lock Flag.
0: PLL Frequency is not locked.
1: PLL Frequency is locked.
Bit 3:
Bit 2:
RESERVED. Read = 0b. Must Write 0b.
PLLSRC: PLL Reference Clock Source Select Bit.
0: PLL Reference Clock Source is Internal Oscillator.
1: PLL Reference Clock Source is External Oscillator.
PLLEN: PLL Enable Bit.
0: PLL is held in reset.
1: PLL is enabled. PLLPWR must be ‘1’.
PLLPWR: PLL Power Enable.
Bit 1:
Bit 0:
0: PLL bias generator is de-activated. No static power is consumed.
1: PLL bias generator is active. Must be set for PLL to operate.
SFR Definition 16.7. PLL0DIV: PLL Pre-divider
SFR Page:
F
SFR Address: 0xA9
R/W
R/W
–
R/W
–
R/W
PLLM4
Bit4
R/W
PLLM3
Bit3
R/W
PLLM2
Bit2
R/W
PLLM1
Bit1
R/W
Reset Value
–
Bit7
PLLM0 00000001
Bit0
Bit6
Bit5
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bits 4–0: PLLM4–0: PLL Reference Clock Pre-divider.
These bits select the pre-divide value of the PLL reference clock. When set to any non-zero
value, the reference clock will be divided by the value in PLLM4–0. When set to ‘00000b’,
the reference clock will be divided by 32.
180
Rev. 1.0
SILICON [ SILICON ]
