C8051F360/1/2/3/4/5/6/7/8/9
The replacement algorithm is selected with the Cache Algorithm bit, CHALGM (CCH0TN.3). When
CHALGM is cleared to ‘0’, the cache will use the rebound algorithm to replace cache locations. The
rebound algorithm replaces locations in order from the beginning of cache memory to the end, and then
from the end of cache memory to the beginning. When CHALGM is set to ‘1’, the cache will use the
pseudo-random algorithm to replace cache locations. The pseudo-random algorithm uses a pseudo-ran-
dom number to determine which cache location to replace. The cache can be manually emptied by writing
a ‘1’ to the CHFLUSH bit (CCH0CN.4).
Valid
Bit
Address
Data
Prefetch Data
VL
LINEAR TAG
LINEAR SLOT
V0
V1
V2
TAG 0
TAG 1
TAG 2
SLOT 0
SLOT 1
SLOT 2
Cache Data
V27
V28
V29
V30
V31
TAG 27
TAG 28
TAG 29
TAG 30
TAG 31
SLOT 27
SLOT 28
SLOT 29
SLOT 30
SLOT 31
A14
A2 A1 A0
0
0
1
1
0
1
0
1
Byte 0
Byte 1
Byte 2
Byte 3
TAG = 13 MSBs of Absolute FLASH Address
SLOT = 4 Instruction
Data Bytes
Figure 14.2. Branch Target Cache Organization
14.2. Cache and Prefetch Optimization
By default, the branch target cache is configured to provide code speed improvements for a broad range of
circumstances. In most applications, the cache control registers should be left in their reset states.
Sometimes it is desirable to optimize the execution time of a specific routine or critical timing loop. The
branch target cache includes options to exclude caching of certain types of data, as well as the ability to
pre-load and lock time-critical branch locations to optimize execution speed.
The most basic level of cache control is implemented with the Cache Miss Penalty Threshold bits, CHM-
STH (CCH0TN.1–0). If the processor is stalled during a prefetch operation for more clock cycles than the
number stored in CHMSTH, the requested data will be cached when it becomes available. The CHMSTH
bits are set to zero by default, meaning that any time the processor is stalled, the new data will be cached.
If, for example, CHMSTH is equal to 2, any cache miss causing a delay of 3 or 4 clock cycles will be
cached, while a cache miss causing a delay of 1–2 clock cycles will not be cached.
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