C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 14.2. CCH0TN: Cache Tuning
SFR Page:
F
SFR Address: 0xC9
R/W
R/W
R/W
Bit5
R/W
Bit4
R/W
R/W
R/W
R/W
Bit0
Reset Value
CHMSCTL
Bit6
CHALGM CHFIXM
CHMSTH
Bit1
00000100
Bit7
Bit3
Bit2
Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1).
These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first
be latched by reading the CHMSCTH bits in the CCH0MA Register (See SFR Definition
14.4).
Bit 3:
Bit 2:
CHALGM: Cache Algorithm Select.
This bit selects the cache replacement algorithm.
0: Cache uses Rebound algorithm.
1: Cache uses Pseudo-random algorithm.
CHFIXM: Cache Fix MOVC Enable.
This bit forces MOVC writes to the cache memory to use slot 0.
0: MOVC data is written according to the current algorithm selected by the CHALGM bit.
1: MOVC data is always written to cache slot 0.
Bits 1–0: CHMSTH: Cache Miss Penalty Threshold.
These bits determine when missed instruction data will be cached.
If data takes longer than CHMSTH clocks to obtain, it will be cached.
150
Rev. 1.0
SILICON [ SILICON ]
