BATTERY PROTECTION IC FOR SINGLE-CELL PACK
S-8261 Series
Rev.1.9_00
7. Delay Circuits
The detection delay times are determined by dividing a clock of the approximately 3.5 kHz with the
counter.
Remark 1. The detection delay time for overcurrent 2 (tIOV2) and load short-circuiting (tSHORT) start when
the overcurrent 1 (VIOV1) is detected. When the overcurrent 2 (VIOV2) or load short-circuiting
(VSHORT) is detected over the detection delay time for each of them (= tIOV2 or tSHORT) after the
detection of overcurrent 1 (VIOV1), the S-8261 Series turns the FET off within tIOV2 or tSHORT of
each detection.
VDD
DO pin
tD
0≦tD≦tIOV2
VSS
Overcurrent 2 detection delay time (tIOV2
VDD
)
Time
VIOV2
VM pin
VIOV1
VSS
Time
Figure 6
2. When the overcurrent is detected and continues for longer than the overdischarge detection
delay time (tDL) without releasing the load, the condition changes to the power-down condition
when the battery voltage falls below the overdischarge detection voltage (VDL). When the
battery voltage falls below the overdischarge detection voltage (VDL) due to the overcurrent,
the S-8261 Series turns the discharging control FET off by the overcurrent detection. In this
case the recovery of the battery voltage is so slow that if the battery voltage after the
overdischarge detection delay time (tDL) is still lower than the over discharge detection
voltage (VDL), the S-8261 Series shifts to the power-down condition.
8. DP Pin
The DP pin is a test pin for delay time measurement and it should be open in the actual application. If a
capacitor whose capacitance is larger than 1000 pF or a resister whose resistance is less than 1 MΩ is
connected to this pin, error may occur in the delay times or in the detection voltages.
9. 0 V Battery Charging Function “Available”
This function is used to recharge the connected battery whose voltage is 0 V due to the self-discharge.
When the 0 V battery charge starting charger voltage (V0CHA) or higher is applied between EB+ pin and
EB− pin by connecting a charger, the charging control FET gate is fixed to VDD pin voltage. When the
voltage between the gate and source of the charging control FET becomes equal to or higher than the
turn-on voltage due to the charger voltage, the charging control FET is turned on to start charging. At
this time, the discharging control FET is off and the charging current flows through the internal parasitic
diode in the discharging control FET. When the battery voltage becomes equal to or higher than the
overdischarge release voltage (VDU), the S-8261 Series enters the normal condition.
Caution Some battery providers do not recommend charging for completely self-discharged
battery. Please ask battery providers before determine whether to enable or inhibit the
0 V battery charging function.
Remark The 0 V battery charge function has higher priority than the abnormal charge current detection
function. Consequently, a product with the 0 V battery charging function is enabled charges
a battery forcibly and abnormal charge current cannot be detected when the battery voltage is
low.
20
Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
