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SAB82525H-V21 参数 Datasheet PDF下载

SAB82525H-V21图片预览
型号: SAB82525H-V21
PDF下载: 下载PDF文件 查看货源
内容描述: 高层次的串行通信控制器扩展 [High-Level Serial Communication Controller Extended]
分类和应用: 通信控制器
文件页数/大小: 126 页 / 741 K
品牌: SIEMENS [ Siemens Semiconductor Group ]
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SAB 82525  
SAB 82526  
SAF 82525  
SAF 82526  
Pin Definitions and Functions (cont’d)  
Pin No.  
Symbol Input (I)  
Output (O)  
Function  
P-LCC P-MQFP  
28  
33  
oD  
Interrupt Request  
INT  
The signal is activated, when the HSCX requests an  
interrupt.  
The CPU may determine the particular source and cause of  
the interrupt by reading the HSCX’s interrupt status  
registers. (ISTA, EXIR).  
INT is an open drain output, thus the interrupt requests  
outputs of several HSCX’s can be connected to one  
interrupt input in a "wired-or" combination.  
This pin must be connected to a pull-up resistor.  
30  
29  
35  
34  
DACKA I  
DACKB  
DMA Acknowledge (channel A/channel B)  
When low, this input signal from the DMA controller notifies,  
the HSCX, that the requested DMA cycle controlled via  
DRQxx (pins 37–40) is in progress, i.e. the DMA controller  
has achieved bus mastership from the CPU and will start  
data transfer cycles (either read or write).  
Together with RD, if DMA has been requested from the  
receiver, or with WR, if DMA has been requested from the  
transmitter, this input works like CS to enable a data byte to  
be read from or written to the top of the receive or transmit  
FIFO of the specified channel.  
If DACKn is active, the input on pins A0–A6 is ignored and  
the FIFOs are implicitly selected.  
If the DACKn signals are not used, these pins must be  
connected to VDD.  
34  
31  
39  
36  
AxCLK  
A
AxCLK  
B
I
Alternative Clock (channel A/channel B)  
These pins realize several input functions. Depending on  
the selected clock mode, they may supply either a  
– CD (= Carrier Detect) modem control or general purpose  
input.  
This pin can be programmed to functions as receiver  
enable if the "auto start" feature is selected (CAS bit in  
XBCH set). The state at this pin can be read from VSTR  
register,  
– or a receive strobe signal (clock mode 1)  
– or a frame synchronization signal in time-slot oriented  
operation mode (clock mode 5)  
– or, together with RxCLK, a crystal connection for the  
internal oscillator (clock mode 4, 6, 7, AxCLK A only).  
Semiconductor Group  
13  
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