SAB 82525
SAB 82526
SAF 82525
SAF 82526
– Phase Shift
In the case the DPLL detects an edge in the data stream in the range of DPLL count 5 to 10
(Phase Shift) and this is the only one in the assumed bit cell period, then the DPLL receive
clock phase is shifted by a certain DPLL count value.
Phase Shift
Assumed Bit Cell
DPLL Input
Receive Data
DPLL Count
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
DPLL
Phase Correction
Phase Adjust+1
Phase Shift+7
Phase Adjust - 1
DPLL Output
Receive Clock
+
-
ITD05884
Figure 28d
Synchronization of the Data Clock in DPLL Mode: Interference Rejection and Phase
Adjustment
The DPLL value and its corresponding phase shift in degree is listed below for the HSCX
versions VA3 and V2.1:
HSCX Version
VA3
DPLL Count
Phase Shift
180o
8
7
V2.1
157,5o
Note: The operating characteristics of the DPLL therefore allow a phase jitter of 18.75% of the
frequency.
Semiconductor Group
59
SIEMENS [ Siemens Semiconductor Group ]
