SAB
SAB
SAF
SAF
82525
82526
82525
82526
Normally 33 pF capacitors are used for frequencies below 10 MHz and 22 pF capacitors are
used for frequencies above 10 MHz.
RxCLKA
AxCLKA
ITS01450
To guarantee oscillation use the capacitances which are specified by the crystal manufacturer.
5.2 Clock Recovery (DPLL)
The HSCX offers the advantage of recovering the receive clock from the receive data by
means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
information via the serial link.
For this purpose, the DPLL is supplied with a reference clock from BRG which is 16 times the
data clock rate (clock mode 2, 3, 6, 7). Additionally, the transmit clock may be obtained dividing
the output of the BRG by a constant factor of 16 (clock mode 2, 6; TSS bit in CCR2 set) or also
directly from the DPLL (clock mode 3, 7).
Interference Rejection
RxD
DPLL CLK
Rec. Data
1
1
ITT06028
Figure 28a
The DPLL circuits implemented in the HSCX are optimized with respect to the HDLC protocol.
The main task of the DPLL is to derive a receive clock and to adjust its phase to the incoming
data stream in order to enable the bit sampling in the middle of a bit-cell with the falling edge
of the receive clock. For this purpose, edges in the receive data, indicating the begin of a bit-
cell, are necessary.
When using the NRZI encoding, the zero insert/zero delete method ensures that a sufficient
number of edges occur in the data stream during the reception of an HDLC frame. Furthermore
a completely new "one insertion" mechanism has been implemented with the HSCX, which
also guarantees sufficient number of edges when using NRZ encoding (especially for bus
configurations,
see chapter 6.5
for details).
Semiconductor Group
57
SIEMENS [ Siemens Semiconductor Group ]
