SAB 82525
SAB 82526
SAF 82525
SAF 82526
The following functions have been implemented to facilitate a high-speed and reliable
synchronization (see figures 28).
– Interference Rejection
In the case where two or more edges appear in the data stream within a time period of 16
reference clocks, these are detected as interference without performing additional
adjustments.
Phase Adjustment
φ
φ
φ
Rx D
DPLL CLK
ITT00241
Rec. Data
0
1
Figure 28b
– Phase Adjustment
In the case where an edge with a phase angle of 20 to 112 degrees appears in the data stream
within the time window, the phase will be adjusted by 1/16 of the data clock.
Receiver
Receive Data
Receive
Clock
DPLL
Reference Clock =
16 x Nominal
Data Clock Rate
ITS06029
Figure 28c
Semiconductor Group
58
SIEMENS [ Siemens Semiconductor Group ]
