SAB
SAB
SAF
SAF
1.2 System Integration
General Aspects
Figure 2
gives a general overview of the system integration of HSCX.
82525
82526
82525
82526
INT
System Bus
CS
DRQTA, DRQRA, DACKA
DMA
Controller
DRQTB, DRQRB, DACKB
HSCX
DATA
Serial
Serial
Channel B Channel A
ITS00947
Figure 2
General System Integration of HSCX
The HSCX bus interface consists of an 8-bit bidirectional data bus (D0–D7), seven address
line inputs (A0–A6), three control inputs (RD/DS, WR/R/W, CS), one interrupt request output
(INT) and a 4-channel DMA interface (DRQTA, DRQRA, DACKA, DRQTB, DRQRB, DACKB).
Mode input pins (strapping options) allow the bus interface to be configured for either Siemens/
Intel or Motorola environment.
Generally, there are two types of transfers occurring via the system bus:
– command/status transfers, which are always controlled by the CPU. The CPU sets the
operation mode (initialization), controls function sequences and gets status information by
writing or reading the HSCX’s registers (via CS, WR or RD, and register address via A0-A6).
– data transfers, which are effectively performed by DMA without CPU interaction using the
HSCX’s DMA interface (DMA mode). Optionally, interrupt controlled data transfer can be
done by the CPU (interrupt mode).
Semiconductor Group
17
Status
Memory
CPU
Command
SIEMENS [ Siemens Semiconductor Group ]
