SAB 82525
SAB 82526
SAF 82525
SAF 82526
Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
P-LCC P-MQFP
36
32
41
37
TxCLK A I/O
TxCLK B
Transmit Clock (channel A/channel B)
The functions of these pins depend on the programmed
clock mode, provided that the TSS bit in the CCR2 register
is reset. Programmed as inputs (if the TIO bit in CCR2 is
reset), they may supply either
– the transmit clock for the respective channel (clock
mode 0, 2, 6),
– or a transmit strobe signal (clock mode 1).
Programmed as outputs (if the TIO bit in CCR2 is set), the
TxCLK pins supply either the
– transmit clock of the respective channel which is
generated either
from the baudrate generator (clock mode 2, 6; TSS bit in
CCR2 set),
or from the DPLL circuit (clock mode 3, 7),
or from the crystal oscillator (clock mode 4)
– or a tristate control signal indicating the programmed
transmit time-slot (clock mode 5).
35
33
40
38
RxCLK A I
RxCLK B
Receive Clock (channel A/channel B)
The functions of these pins also depend on the
programmed clock mode. In each channel, RxCLK may
supply either
– the receive clock (clock mode 0)
– or the receive and transmit clock (clock mode 1, 5)
– or the clock for the baudrate generator (clock mode 2,
3),
– or a crystal connection for the internal
oscillator (clock mode 4,6,7, RxCLK A/B together
with AxCLK A)
39
37
44
42
DRQRA O
DRQRB
DMA Request Receiver (channel A/channel B)
The receiver of the HSCX requests a DMA data transfer by
activating this line.
The DRQRn remains high as long as the receive FIFO
requires data transfers, thus always blocks of data (32, 16,
8 or 4 bytes) are transferred.
DRQRn is deactivated immediately following the falling
edge of the last read cycle.
Semiconductor Group
14
SIEMENS [ Siemens Semiconductor Group ]
