SAB 82525
SAB 82526
SAF 82525
SAF 82526
Channel A
A0-A6
D0-D7
RxDA
TxDA
RTSA
LAP
Controller
Decoder
Collision
Detection
SP-REG
CTSA/
CxDA
RD/IC1
WR/IC0
CS
DPLL
Data
Link
Controller
Transmit
FIFO
RxCLKA
BRG
TSA
Clock
Controll
ALE/IMO
INT
Receive
FIFO
AxCLKA
TxCLKA
µP Bus
Interface
RES
IM1
TxCLKB
AxCLKB
RxCLKB
DRQTA
DRQRA
DACKA
DMA
Interface
CTSB/
CxDB
DRQTB
DRQRB
DACKB
RTSB
TxDB
RxDB
Channel B
ITB00946
Figure 1
Block Diagram SAB 82525/SAB 82526
The HSCX SAB 82526 comprises one (channel B), the SAB 82525 two completely
independent full-duplex HDLC channels (channel A and channel B), supporting various layer-1
functions by means of internal oscillator, Baud Rate Generator (BRG), Digital Phase Locked
Loop (DPLL), and Time-Slot Assignment (TSA) circuits.
Furthermore, layer-2 functions are performed by an on-chip LAP (Link Access Procedure, e.g.
LAPB or LAPD) controller.
Semiconductor Group
16
SIEMENS [ Siemens Semiconductor Group ]
