SAB 82525
SAB 82526
SAF 82525
SAF 82526
CIE … Clear To Send Interrupt Enable
Any state transition at the CTS input pin may cause an interrupt which is indicated in the
EXIR register (CSC bit). The actual state at the CTS pin can be determined reading the CTS
bit of the STAR register.
0 … disable
1 … enable
RIE … Receive Frame Start Interrupt Enable
When, the RFS interrupt (via EXIR) is enabled!
DIV … Data Inversion
Only valid if NRZ data encoding is selected. Data is transmitted and received inverted.
XCS0, RCS0 … Transmit/Receive Clock Shift, Bit 0
Together with bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the clock shift relative to
the frame synchronization signal of the transmit (receive) time-slot can be adjusted.
A clock shift of 0 … 7 bits is programmable (clock mode 5 only!).
Semiconductor Group
101
SIEMENS [ Siemens Semiconductor Group ]
