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SAB82525N 参数 Datasheet PDF下载

SAB82525N图片预览
型号: SAB82525N
PDF下载: 下载PDF文件 查看货源
内容描述: 高层次的串行通信 [High-Level Serial Communication]
分类和应用: 通信
文件页数/大小: 126 页 / 741 K
品牌: SIEMENS [ Siemens Semiconductor Group ]
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SAB 82525  
SAB 82526  
SAF 82525  
SAF 82526  
ODS … Output Driver Select  
Defines the function of the transmit data pins (T × DA, T × DB)  
0. . .T × D pins are open drain outputs  
1. . .T × D pins are push-pull outputs  
Note: Since in time-slot oriented systems the T × D pin is not tristated automatically out of the  
programmed time-slot, the T × D pin should be configured as open drain in time-slot  
oriented bus systems.  
ITF/OIN … Interframe Time Fill/One Insertion  
The function of this bit depends on the selected serial port configuration (bit SC0)  
Point-to-point configurations: ITF  
Determines the idle (= no data to send) state of the transmit data pins (T × DA, T × DB)  
0 … Continuous IDLE sequences are output (T × D pins remain in the "1" state)  
1 … Continuous FLAG sequences are output ("01111110" bit patterns)  
Bus configurations: OIN  
In bus configurations, the ITF is implicitly set to 0, i.e. continuous "1"s are transmitted,  
and data encoding is NRZ!  
When this bit is set, a "ONE" insertion (deletion) mechanism is activated, inserting a "1"  
after seven consecutive "0"s in the transmit data stream or deleting a "1" in the receive  
data stream.  
Similar to the HDLC’s bit-stuffing mechanism (inserting a "0" after five consecutive "1"s),  
this method proves to be advantageous when the receive clock is recovered from the  
receive data stream by means of DPLL, because it is guaranteed that at least after seven  
bits a transition occurs in the receive data in case of long "0" sequences!  
CM2, CM1, CMO … Clock Mode  
Selects one of the 8 different clock modes  
000  
clock mode 0  
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111  
clock mode 7  
Semiconductor Group  
105  
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