HYB 5118160BSJ-50/-60
HYB 3118160BSJ-50/-60
1M × 16 DRAM
Notes
1. All voltages are referenced to VSS.
2. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once
or less during a fast page mode cycle (tPC).
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume tT = 5 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with a load equivalent to 100 pF and at VOH = 2.0 V (IOH = – 2 mA), VOL = 0.8 V
(IOL = 2 mA).
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC
.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.) and tOEZ (MAX.) define the time at which the outputs achieve the open-circuit condition
and are not referenced to output voltage levels.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle
and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if
t
RWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD (MIN.) and tCPWD > tCPWD (MIN.) , the cycle is a read-
write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets
of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
Semiconductor Group
10
1998-10-01
SIEMENS [ Siemens Semiconductor Group ]
