SiHD5N50D
D Series Power MOSFET
Peak Diode Recovery
dV/dt
Test Circuit
+
Circuit layout considerations
•
Low
stray
inductance
•
Ground
plane
•
Low leakage inductance
current transformer
D.U.T.
-
+
-
-
+
R
g
•
•
•
•
dV/dt controlled by R
g
Driver
same
type as D.U.T.
I
SD
controlled by duty factor “D”
D.U.T. - device under test
+
-
V
DD
Driver gate drive
P.W.
Period
D=
P.W.
Period
V
GS
= 10 V
a
D.U.T. l
SD
waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V
DS
waveform
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Inductor current
Body diode forward drop
Ripple
≤
5 %
Note
a. V
GS
= 5 V for logic level devices
I
SD
Fig. 18 - For N-Channel
6/9
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