SX1232
WIRELESS & SENSING
DATASHEET
5.3. Digital IO Pins Mapping
Six general purpose IO pins are available on the SX1232, and their configuration in Continuous or Packet mode is
controlled through RegDioMapping1 and RegDioMapping2.
Table 27 DIO Mapping, Continuous Mode
DIOx Mapping
Sleep
Standby
FSRx/Tx
Rx
Tx
TxReady
-
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
-
-
-
SyncAddress
Rssi / PreambleDetect
RxReady
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
TxReady
-
-
-
Dclk
Rssi / PreambleDetect
-
-
-
-
-
-
-
-
-
Data
Data
Data
Data
Timeout
Rssi / PreambleDetect
-
-
-
-
TempChange / LowBat
TempChange / LowBat
TempChange / LowBat
PllLock
-
-
-
-
TimeOut
-
-
-
ModeReady
ClkOut
ModeReady
ClkOut
ClkOut if RC
-
PllLock
Rssi / PreambleDetect
ModeReady
-
ModeReady
Table 28 DIO Mapping, Packet Mode
DIOx Mapping
Sleep
Standby
FSRx/Tx
Rx
Tx
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
-
-
PayloadReady
CrcOk
PacketSent
-
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
-
-
TempChange / LowBat
TempChange / LowBat
FifoLevel
FifoEmpty
FifoFull
FifoLevel
FifoLevel
FifoEmpty
FifoFull
FifoEmpty
FifoFull
-
FifoFull
FifoFull
FifoFull
-
RxReady
TimeOut
SyncAddress
-
FifoFull
FifoFull
FifoFull
FifoFull
FifoEmpty
FifoEmpty
FifoEmpty
-
TxReady
FifoEmpty
FifoEmpty
FifoEmpty
FifoEmpty
FifoEmpty
FifoEmpty
TempChange / LowBat
PllLock
-
TempChange / LowBat
-
-
-
TimeOut
Rssi / PreambleDetect
-
-
ClkOut if RC
-
ClkOut
ClkOut
-
PllLock
-
Data
ModeReady
ModeReady
Rev 3 - August 2012
Page 53
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