E0C88365
q
LCD Circuit
The Typ. values of the LCD drive voltage shown in the following table shift in difference of panel load (panel size, drive duty,
display segment number). Therefore, these should be evaluated by connecting to the actual panel to be used. Moreover, if
the display is uneven with a large panel load, connect a resistor (R
1
) between the V
SS
and V
C1
terminal.
Item
LCD drive voltage
(Unless otherwise specified: V
DD
= V
C2
(LCX = FH) + 0.3 to 5.5V, V
SS
= 0V, Ta = 25°C, C1–C9 = 0.1µF)
Symbol
Condition
Min.
Typ.
Max.
Unit Note
1
–
0.22V
C5
V
V
C1
*
0.18V
C5
–
–
V
V
C2
*
2
0.39V
C5
0.43V
C5
–
3
–
V
V
C3
*
0.59V
C5
0.63V
C5
–
–
V
V
C4
*
4
0.80V
C5
0.84V
C5
–
5
3.89
V
V
C5
*
LCX = 0H
–
3.96
V
LCX = 1H
–
4.04
V
LCX = 2H
–
4.11
V
LCX = 3H
–
4.18
V
LCX = 4H
–
4.26
V
LCX = 5H
–
4.34
V
LCX = 6H
–
4.42
V
LCX = 7H
–
Typ×0.94
Typ×1.06
4.50
V
LCX = 8H
–
4.58
V
LCX = 9H
–
4.66
V
LCX = AH
–
4.74
V
LCX = BH
–
4.82
V
LCX = CH
–
4.90
V
LCX = DH
–
4.99
V
LCX = EH
–
5.08
V
LCX = FH
–
Connects 1 MΩ load resistor between V
SS
and V
C1
. (without panel load)
Connects 1 MΩ load resistor between V
SS
and V
C2
. (without panel load)
Connects 1 MΩ load resistor between V
SS
and V
C3
. (without panel load)
Connects 1 MΩ load resistor between V
SS
and V
C4
. (without panel load)
Connects 1 MΩ load resistor between V
SS
and V
C5
. (without panel load)
∗1
∗2
∗3
∗4
∗5
q
SVD Circuit
Item
SVD voltage
(Unless otherwise specified: V
DD
= 2.2 to 5.5V, V
SS
= 0V, Ta = 25°C)
Symbol
Condition
Min.
Typ.
Max.
Unit Note
V
SVD
Level 1
→
Level 0
1.82
V
–
Level 2
→
Level 1
2.00
V
–
Level 3
→
Level 2
2.18
V
–
Level 4
→
Level 3
2.36
V
–
Level 5
→
Level 4
Typ×0.92
2.54
Typ×1.08
V
–
Level 6
→
Level 5
2.72
V
–
Level 7
→
Level 6
2.90
V
–
Level 8
→
Level 7
3.08
V
–
Level 9
→
Level 8
3.26
V
–
Level 10
→
Level 9
3.45
V
–
Level 11
→
Level 10
3.65
V
–
Level 12
→
Level 11
3.85
V
–
Typ×0.88
Typ×1.12
Level 13
→
Level 12
4.05
V
–
Level 14
→
Level 13
4.25
V
–
Level 15
→
Level 14
4.50
V
–
q
Analog Comparator Circuit
(Unless otherwise specified: V
DD
= 2.2 to 5.5V, V
SS
= 0V, Ta = 25°C)
Symbol
Condition
Min.
Typ.
Max.
Unit Note
V
CMIP
Non-inverted input (CMPP)
0.7
–
V
DD
-0.7
V
6
V
CMIM
Inverted input (CMPM)
0.7
–
V
DD
-0.7
V
6
V
CMOF
V
CMIP
= 0.7 V to V
DD
- 0.7 V
–
–
20
mV
6
V
CMIM
= 0.7 V to V
DD
- 0.7 V
Analog comparator stability time
t
CMP1
–
–
1
mS
7
Analog comparator response time
t
CMP2
V
CMIP
= 0.7 V to V
DD
- 0.7 V
–
–
2
mS
6
V
CMIM
= 0.7 V to V
DD
- 0.7 V
8
V
CMIP
= V
CMIM
±
0.025 V
Note) 6 When "without pull-up resistor" (comparator input terminal) is selected by mask option.
7 Stability time is the time from turning the circuit ON until the circuit is stabilized.
8 Response time is the time that the output result responds to the input signal.
Item
Analog comparator
operating voltage input range
Analog comparator offset voltage
5
SEIKO [ SEIKO EPSON CORPORATION ]
