E0C88365
■ BLOCK DIAGRAM
Core CPU E0C88
OSC1, 2
Oscillator
Interrupt Controller
Input Port
OSC3, 4
MCU/MPU
BREQ (K11)
BACK (R51)
K00–K07
K10 (EVIN)
K11 (BREQ)
System Controller
Reset/Test
RESET
TEST
I/O Port
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
Watchdog Timer
Serial Interface
P14, P15 (CMPP0, CMPM0)
P16, P17 (CMPP1, CMPM1)
Analog
Comparator
Programmable Timer
/Event Counter
EVIN (K10)
P00–P07 (D0–D7)
External
Memory
Interface
Clock Timer
R00–R07, R10–R17, R20–R22 (A0–A7, A8–A15, A16–A18)
R23, R24 (RD, WR)
R30–R33 (CE0–CE3)
R25, R26 (CL, FR)
R27 (TOUT)
Stopwatch Timer
Sound Generator
Output Port
R34 (FOUT)
V
DD
SS
D1
C1–VC5
CA–CE
R35–R37
V
R40–R47
Power Generator
V
R50 (BZ)
V
R51 (BACK)
SEG0–SEG79
COM0–COM17
LCD Driver
Supply Voltage Detector
RAM
ROM
3K byte
64K byte
2
SEIKO [ SEIKO EPSON CORPORATION ]
