E0C88365D 参数 Datasheet PDF下载

E0C88365

s

ELECTRICAL CHARACTERISTICS

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Absolute Maximum Ratings

Item

Power voltage

Liquid crystal power voltage

Input voltage

Output voltage

High level output current

Symbol

V

DD

V

C5

V

I

V

O

I

OH

Condition

Rated value

-0.3 to +7.0

-0.3 to +7.0

-0.3 to V

DD

+ 0.3

-0.3 to V

DD

+ 0.3

-5

-20

5

20

-40 to +85

-65 to +150

(V

SS

= 0V)

Unit Note

V

–

V

–

V

–

V

1

mA

–

mA

–

mA

–

mA

–

°C

–

°C

–

–

–

–

–

1 terminal

Total of all terminals

I

OL

1 terminal

Low level output current

Total of all terminals

Topr –

Operating temperature

Tstg

–

Storage temperature

Note) 1 Case that to Nch open drain output by the mask option is included.

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Recommended Operating Conditions

(V

SS

= 0 V, Ta = -40 to 85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit Note

2.2

–

5.5

V

V

DD

–

Operating power voltage

–

30

–

155

kHz

f

OSC1

V

DD

= 2.2 to 5.5 V

Operating frequency

2

f

OSC3

0.03

–

2.5

MHz

–

C1

–

0.1

–

µF

–

Capacitor between V

D1

and V

SS

–

Capacitor between V

C1

and V

SS

C2

–

0.1

–

µF

–

–

Capacitor between V

C2

and V

SS

C3

–

0.1

–

µF

–

–

Capacitor between V

C3

and V

SS

C4

–

0.1

–

µF

–

–

Capacitor between V

C4

and V

SS

C5

–

0.1

–

µF

–

–

Capacitor between V

C5

and V

SS

C6

–

0.1

–

µF

–

–

Capacitor between CA and CB

C7

–

0.1

–

µF

–

–

Capacitor between CA and CC

C8

–

0.1

–

µF

–

–

Capacitor between CD and CE

C9

–

0.1

–

µF

–

–

Resistor between V

C1

and V

SS

R1

–

100

–

kΩ

–

3

Note) 2 When an external clock is input from the OSC1 terminal by the mask option, do not connect anything to the OSC2 terminal.

3 It is necessary when a large panel is used. The resistance value should be decided by connecting it to the actual panel to be used.

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DC Characteristics

(Unless otherwise specified: V

DD

= 2.2 to 5.5V, V

SS

= 0V, Ta = -40 to 85°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit Note

V

–

V

DD

High level input voltage (1)

V

IH1

Kxx, Pxx, MCU/MPU

0.8V

DD

–

V

–

V

IL1

0

0.2V

DD

Low level input voltage (1)

Kxx, Pxx, MCU/MPU

–

V

–

V

IH2

V

DD

1.6

High level input voltage (2)

OSC1

4

V

–

V

IL2

0.6

0

Low level input voltage (2)

OSC1

4

V

–

V

T+

0.9V

DD

0.5V

DD

High level schmitt input voltage

RESET

–

V

–

V

T-

0.1V

DD

0.5V

DD

Low level schmitt input voltage

RESET

–

mA

I

OH1

–

–

-0.5

High level output current (1)

P1x, Rxx, V

OH

= 0.9 V

DD

–

I

OL1

P1x, Rxx, V

OL

= 0.1 V

DD

mA

0.5

–

–

Low level output current (1)

–

I

OH2

P0x

mA

–

–

-0.1

High level output current (2)

–

I

OL2

P0x

mA

0.1

–

–

Low level output current (2)

–

I

LI

Kxx, Pxx, RESET, MCU/MPU

µA

-1

–

1

Input leak current

–

I

LO

Pxx, Rxx

µA

-1

–

1

Output leak current

–

R

IN

Kxx, Pxx, RESET, MCU/MPU

kΩ

100

–

500

Input pull-up resistance

5

C

IN

Kxx, Pxx

pF

–

–

15

Input terminal capacitance

–

V

IN

= 0 V, f = 1 MHz, Ta = 25°C

I

SEGH

SEGxx, COMxx, V

SEGH

= V

C5

-0.1 V

µA

–

–

-5

Segment/Common output current

–

I

SEGL

SEGxx, COMxx, V

SEGL

= 0.1 V

µA

5

–

–

–

Note) 4 When external clock is selected by mask option.

5 When addition of pull-up resistor is selected by mask option.

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