E0C6247
q
Serial Interface AC Characteristics
Clock synchronous master mode
• During 32kHz (OSC1) operation
Characteristic
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
(Condition: V
DD
=1.5V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
)
Symbol
Min.
Typ.
Max.
Unit
t
smd
5
µsec
t
sms
10
µsec
5
t
smh
µsec
• During 1MHz (OSC3) operation
Characteristic
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
(Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
)
Symbol
Min.
Typ.
Max.
Unit
t
smd
t
sms
t
smh
200
400
200
nsec
nsec
nsec
Clock synchronous slave mode
• During 32kHz (OSC1) operation
Characteristic
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
(Condition: V
DD
=1.5V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
)
Symbol
Min.
Typ.
Max.
Unit
t
ssd
10
µsec
t
sss
t
ssh
10
5
µsec
µsec
• During 1MHz (OSC3) operation
Characteristic
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
(Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH1
=0.8V
DD
, V
IL1
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
)
Symbol
Min.
Typ.
Max.
Unit
t
ssd
500
nsec
t
sss
400
nsec
200
t
ssh
nsec
Asynchronous mode
Symbol
Min.
Characteristic
Start bit detection error time
*
1
t
sa
1
0
Erroneous start bit detection range time
*
2
t
sa
2
9t/16
∗1
Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
∗2
Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again after a start bit
has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit detection circuit is reset
and goes into a wait status until the next start bit. (Time as far as AC is excluded.)
(Condition: V
DD
=1.5V, V
SS
=0V, Ta=25°C)
Typ.
Max.
Unit
t/16
sec
10t/16
sec
<Clock synchronous master mode>
SCLK OUT
V
OH
V
OL
<Asynchronous mode>
SIN
Start bit
Stop bit
t
smd
SOUT
V
OH
V
OL
t
sa
1
Sampling
clock
t
sms
SIN
V
IH1
V
IL1
t
smh
Erroneous
start bit
detection signal
t
<Clock synchronous slave mode>
SCLK IN
V
IH1
V
IL1
t
sa
2
SOUT
t
ssd
V
OH
V
OL
t
sss
t
ssh
V
IH1
V
IL1
SIN
9
SEIKO [ SEIKO EPSON CORPORATION ]
