欢迎访问ic37.com |
会员登录 免费注册
发布采购

E0C6247F 参数 Datasheet PDF下载

E0C6247F图片预览
型号: E0C6247F
PDF下载: 下载PDF文件 查看货源
内容描述: [4-BIT, MROM, 1MHz, MICROCONTROLLER, PQFP16, PLASTIC, QFP-160]
分类和应用: 时钟外围集成电路
文件页数/大小: 12 页 / 123 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
 浏览型号E0C6247F的Datasheet PDF文件第4页浏览型号E0C6247F的Datasheet PDF文件第5页浏览型号E0C6247F的Datasheet PDF文件第6页浏览型号E0C6247F的Datasheet PDF文件第7页浏览型号E0C6247F的Datasheet PDF文件第9页浏览型号E0C6247F的Datasheet PDF文件第10页浏览型号E0C6247F的Datasheet PDF文件第11页浏览型号E0C6247F的Datasheet PDF文件第12页  
E0C6247
q
External Memory Access AC Characteristics
Read cycle
• During 32kHz (OSC1) operation
(Condition: V
DD
=1.5V, V
SS
=0V, Ta=25°C, V
IH
=0.8V
DD
, V
IL
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
, C
L
=100pF [load capacitance])
Characteristic
Symbol
Min.
Typ.
Max.
Unit
CSx set-up time in read cycle
t
ras
0.15
×
t
c
µsec
CSx hold time in read cycle
0
t
rah
µsec
RD set-up time in read cycle
0.15
×
t
c
t
rds
µsec
RD hold time in read cycle
0
t
rdh
µsec
• During 1MHz (OSC3) operation
(Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH
=0.8V
DD
, V
IL
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
, C
L
=100pF [load capacitance])
Characteristic
Symbol
Min.
Typ.
Max.
Unit
nsec
t
ras
0.15
×
t
c
CSx set-up time in read cycle
CSx hold time in read cycle
RD set-up time in read cycle
RD hold time in read cycle
t
rah
t
rds
t
rdh
0
0.15
×
t
c
0
nsec
nsec
nsec
Write cycle
• During 32kHz (OSC1) operation
(Condition: V
DD
=1.5V, V
SS
=0V, Ta=25°C, V
IH
=0.8V
DD
, V
IL
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
, C
L
=100pF [load capacitance])
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Address set-up time in write cycle
Address hold time in write cycle
Write signal pulse width
Data output set-up time in write cycle
Data output hold time in write cycle
µsec
µsec
µsec
µsec
µsec
t
was
t
wah
t
wp
t
wds
t
wdh
0
5
5
5
5
30
• During 1MHz (OSC3) operation
(Condition: V
DD
=3.0V, V
SS
=0V, Ta=25°C, V
IH
=0.8V
DD
, V
IL
=0.2V
DD
, V
OH
=0.8V
DD
, V
OL
=0.2V
DD
, C
L
=100pF [load capacitance])
Symbol
Min.
Typ.
Max.
Unit
Characteristic
nsec
t
was
0
Address set-up time in write cycle
Address hold time in write cycle
Write signal pulse width
Data output set-up time in write cycle
Data output hold time in write cycle
t
wah
t
wp
t
wds
t
wdh
200
200
200
200
t
c
nsec
nsec
nsec
1,500
nsec
CLK
(Sysyem clock)
V
IH
V
IL
<Reading>
CSx
V
OH
V
OL
t
ras
RD
V
OH
V
OL
t
rah
t
rds
DIN
V
IH
V
IL
t
rdh
<Writing>
CSx
V
OH
V
OL
t
was
WR
V
OH
V
OL
t
wah
t
wp
DOUT
V
IH
V
IL
t
wds
*
1/
t
c: oscillation frequency
t
wdh
8