CF5073 series
PAD LAYOUT
(Unit: µm)
XTN
7
VC
1
XT
6
(1240,1400)
5
HA5073
INHN
2
3
(0,0)
VSS
Chip size: 1.24
×
1.4mm
Chip thickness: 300 ± 30µm
Chip base: V
DD
potential
VDD
4
Q
PAD DESCRIPTION AND DIMENSIONS
Pad dimensions [µm]
Pad No.
Name
I/O
Description
Oscillation frequency control
voltage input pin
Output state control voltage
input pin
(−) supply pin
Output pin
(+) supply pin
Amplifier input pin
Amplifier output pin
Crystal connection pins.
Crystal is connected between XT and XTN.
Output frequency determined by internal
circuit to one of f
O
, f
O
/2, f
O
/4, f
O
/8, f
O
/16, f
O
/32
Function
X
1
2
3
4
5
6
7
VC
INHN
VSS
Q
VDD
XT
XTN
I
I
–
O
–
I
O
Positive polarity (frequency increases with
increasing voltage)
High-impedance output when LOW, pull-up
resistor built-in
134
137
458
1086
1106
829
416
Y
915
295
137
155
772
1263
1260
SEIKO NPC CORPORATION —2
SEIKO [ SEIKO EPSON CORPORATION ]
