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S5PV210AA0-LA40
S5PV210_UM_REV0.00 (Preliminary Spec)
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A/D Converter and Touch Screen Interface
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10-ch multiplexed ADC
Max. 500Ksamples/sec and 12-bit resolution
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Watch Dog Timer
16-bit watch dog timer
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Vectored Interrupt Controller
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Multiple interrupt request inputs, one for each interrupt source, and one interrupt request output for the
processor interrupt request input
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Software can mask out particular interrupt requests
Prioritization of interrupt sources for interrupt nesting
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Power Management
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Clock-off control for individual components
Various low-power modes are available such as Idle, Stop, Deep Stop, Deep Idle and Sleep mode
Sleep mode’s wake up sources are external interrupts, RTC alarm, Tick timer and the key interface.
Stop and Deep Stop mode’s wake up sources are MMC, Touch screen interface, Modem interface, MIPI
HSI and the system timer as well all the wake up sources of Sleep mode.
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Deep Idle mode’s wake up sources are 5.1ch I2S as well all the wake up source of Stop mode.
3.7 SYSTEM OPERATING FREQUENCIES
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ARM CortexTM-A8 core clock rate maximum is 800MHz@ 1.1V and 1GHz@1.2V
System operating clock generation
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MSYS domain clock rate maximum is 200MHz@1.1V
DSYS domain clock rate maximum is 166MHz@1.1V
PSYS domain clock rate maximum is 133MHz@1.1V
NOTES: 1.S5PV210 has four system clock domains called MSYS, DSYS, PSYS and AUDIO. MSYS domain is for CPU
system, 3D engine and Multi Format Codec, while DSYS domain for Display. PSYS domain for Other system
component except low power audio which is in AUDIO domain. Nominal 133/166/200MHz represents that PSYS
system frequency is 133MHz, DSYS system frequency is 166MHz and MSYS system frequency is 200MHz at 1.1V
power level.
2. S5PV210 supports only sync mode between CPU and MSYS system.
3. The voltage of the external Memory & I/O interface depends on the attached device specification. Therefore, the
PMIC should supply an appropriate voltage to the interface.
1.1-14
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