INSTRUCTION SET
S3C4510B
ASSEMBLER SYNTAX
<LDR|STR>{cond}{B}{T} Rd,<Address>
where:
LDR
STR
{cond}
{B}
Load from memory into a register
Store from a register into memory
Two-character condition mnemonic. See Table 3-2.
If B is present then byte transfer, otherwise word transfer
If T is present the W bit will be set in a post-indexed instruction, forcing non-
{T}
privileged mode for the transfer cycle. T is not allowed when a pre-indexed
addressing mode is specified or implied.
Rd
An expression evaluating to a valid register number.
Rn and Rm
Expressions evaluating to a register number. If Rn is R15 then the assembler will
subtract 8 from the offset value to allow for ARM7TDMI pipelining. In this case base
write-back should not be specified.
<Address>can be:
1
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the
expression. This will be a PC relative, pre-indexed address. If the address is out of
range, an error will be generated.
2
3
A pre-indexed addressing specification:
[Rn]
[Rn,<#expression>]{!}
[Rn,{+/-}Rm{,<shift>}]{!}
offset of zero
offset of <expression> bytes
offset of +/- contents of index register,
shifted by <shift>
A post-indexed addressing specification:
[Rn],<#expression>
[Rn],{+/-}Rm{,<shift>}
offset of <expression> bytes
offset of +/- contents of index register,
shifted as by <shift>.
<shift>
{!}
General shift operation (see data processing instructions) but you cannot specify
the shift amount by a register.
Writes back the base register (set the W bit) if! is present.
3-32
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