S3C4510B
UART
UART BAUD RATE EXAMPLES
UART BRG input clock, MCLK2 is the system clock frequency divided by 2.
If the system clock frequency is 50 MHz and MCLK2 is selected, the maximum BRGOUT output clock rate is
MCLK2/16 (= 1.5625 MHz).
UCLK is the external clock input pin for UART0, UART1. UART BRG input clock, MCLK2, UCLK can be selected
by UCCON[6] register.
CNT0
CNT1
MCLK2
UCLK
BRGOUT
12-bit Counter
Divide by 1 or 16
Divide by 16
Sample Clock
SC
NOTE:
CNT0 = UBTDIVn [15:4], CNT1 = UBRDIVn [3:0], SC = ULCON [6]
Figure 10-9. UART Baud Rate Generator (BRG)
Table 10-14. Typical Baud Rates Examples of UART
Baud Rates
(BRGOUT)
1200
MCLK2 = 25 MHz
UCLK = 33 MHz
CNT0
1301
650
324
162
80
CNT1
Freq.
1200.1
Dev.(%)
0.0
CNT0
1735
867
433
216
108
53
CNT1
Freq.
Dev.(%)
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1200.08
0.0064
0.0064
0.0064
0.0064
0.45
2400
2400.2
0.0
2400.15
4800
4807.7
0.2
4800.31
9600
9585.9
- 0.1
0.5
9600.61
19200
19290.1
38109.8
57870.4
111607.1
223214.28
520833.34
19113.15
38580.15
57870.37
115740.74
231481.48
416666.66
38400
40
- 0.8
0.5
0.47
57600
26
35
0.47
115200
230400
460860
13
- 3.1
3.12
13.01
17
0.47
6
8
0.47
2
4
9.59
10-15
SAMSUNG [ SAMSUNG ]
