UART
S3C4510B
UART BAUD RATE COUNT AND CLOCK REGISTERS
For test purpose only, the internal baud rate up counters, BRDCNT0 and BRDCNT1, can be directly accessed
using register addressing. In addition, the baud rate clock can be monitored through the UART data set ready
ports, nUADSR.
If the BRDCLKn monitor value is "1", the baud rate clock can be monitored at the nUADSR pin. If it is "0" (its
default value), or if you write a "0" to the BRDCLKn address, the UARD DSR signal output to the nUADSR port
depends on the current setting of UART control register bit 5.
Table 10-13. BRDCNTn and BRDCLKn Registers
Register
BRDCNT0
BRDCNT1
BRDCLK0
BRDCLK1
Offset Address
0xD018
R/W
W
Description
Reset Value
UART0 baud rate count register
UART1 baud rate count register
UART0 baud rate clock monitor
UART1 baud rate clock monitor
0x0
0x0
0x0
0x0
0xE018
W
0xD01C
W
0xE01C
W
Baud Rate Divisor
(UBRDIVn)
Baud Rate Clock
Compare Logic
Match Generator
Baud Rate up Counter
(URDCNTn)
nUADSR
BRDCLKn
MCLK
Chip Internal
Chip External
Figure 10-8. UART Baud Rate Clock Test Scheme
10-14
SAMSUNG [ SAMSUNG ]
