PROGRAMMER'S MODEL
S3C4510B
The THUMB State Register Set
The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight
general registers, R0–R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR),
and the CPSR. There are banked stack pointers, link registers and Saved Process Status Registers (SPSRs) for
each privileged mode. This is shown in Figure 2-4.
THUMB State General Registers and Program Counter
System & User
FIQ
R0
Supervisor
About
IRG
R0
Undefined
R0
R1
R2
R3
R4
R5
R6
R7
SP
LR
PC
R0
R0
R0
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R3
R3
R3
R3
R3
R4
R4
R4
R4
R4
R5
R5
R5
R5
R5
R6
R6
R6
R6
R6
R7
R7
R7
R7
R7
SP_fiq
LR_fiq
PC
SP_svg
LR_svc
PC
SP_abt
LR_abt
PC
SP_irq
LR_irq
PC
SP_und
LR_und
PC
THUMB State Program Status Registers
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR_fiq
SPSR_svc
SPSR_abt
SPSR_irq
SPSR_und
= banked register
Figure 2-4. Register Organization in THUMB State
2-6
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