SYSTEM MANAGER
S3C4510B
DRAM REFRESH AND EXTERNAL I/O CONTROL REGISTER
The S3C4510B DRAM interface supports the CAS-before-RAS (CBR) refresh mode for EDO/FP DRAM and
auto-refresh for SDRAM. Settings in the DRAM refresh and external I/O control register, REFEXTCON, control
DRAM refresh mode, refresh timings, and refresh intervals. REFEXTCON also contains the 10-bit base pointer
value for the external I/O bank 0.
NOTE
Whenever the S3C4510B CPU writes one of system manager registers, the validity of special register
field (that is, the VSF bit) is automatically cleared and the external bus is disabled. To reactivate external
bus, you must set the VSF bit to "1" using a STMIA instruction. It is recommended that programmers
always use STMIA instructions to write the 10 system manager special registers. The instruction used to
set the VSF bit should always be the last instruction in the register write sequence.
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