SYSTEM MANAGER
S3C4510B
31 30 29
20 19
10 9
8
7
6
4
3
2
1
0
ROM/SRAM/Flash Bank #
Next Pointer
ROM/SRAM/Flash Bank #
Base Pointer
0
0
0
0
0
tACC
tPA PMC
[1:0] Page mode configuration (PMC)
00 = Normal ROM
01 = 4-word page
10 = 8-word page
11 = 16-word page
[3:2] Page address access time (tPA)
00 = 5 cycles
01 = 2 cycles
10 = 3 cycles
11 = 4 cycles
[6:4] Programmable access cycle (tACC)
000 = Disable bank
010 = 3 cycle
110 = 7 cycle
001 = 2 cycles
011 = 4 cycles
111 = Reserved
[19:10] ROM/SRAM/Flash bank # base pointer
This value is the start address of the ROM/SRAM/Flash bank #.
The start address is calculated as ROM/SRAM/FLASH bank #
base pointer << 16.
[29:20] ROM/SRAM/FLASH bank # next pointer
This value is the current bank end address << 16 + 1.
Figure 4-18. ROM/SRAM/FLASH Control Registers (ROMCON0–ROMCON5)
4-36