SYSTEM MANAGER
S3C4510B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1 0
EXTDBWTH
0 0 0
0 DSX3 DSX2 DSX1 DSX0 DSD3 DSD2 DSD1 DSD0 DSR5 DSR4 DSR3 DSR2 DSR1 DSR0
[1:0] Data bus width for ROM/SRAM/FLASH bank 0 (DSR0)
DSR0 is read-only data at the B0SIZE [1:0] pins. DSR0 is used as read-only
because ROM/SRAM/FLASH bank 0 is used to boot the ROM while the data
bus width for ROM/SRAM/FLASH bank 0 is set using B0SIZE [1:0].
00 = Not permitted
01 = Byte (8 bits)
10 = Half-word (16 bits)
11 = Word (32 bits)
[3:2] Data bus width for ROM/SRAM/FLASH bank 1 (DSR1)
[5:4] DSR2, [7:6] DSR3, [9:8] DSR4, [11:10] DSR5
00 = Disable
01 = Byte (8 bits)
10 = Half- word (16 bits)
11 = Word (32 bits)
[13:12] Data bus width for DRAM bank 0 (DSD0)
[15:14] DSD1, [17:16] DSD2, [19:18] DSD3
00 = Disable
01 = Byte (8 bits)
10 = Half-word (16 bits)
11 = Word (32 bits)
[21:20] Data bus width for external I/O bank 0 (DSX0)
[23:22] DSX1, [25:24] DSX2, [27:26] DSX3
00 = Dissable
01 = Byte (8 bits)
10 = Half-word (16 bits)
11 = Word (32 bits)
NOTE:
When you select "Disable", the assigned external I/O
bank access signal is not generated.
Figure 4-17. Data Bus Width Register (EXTDBWTH)
4-34
SAMSUNG [ SAMSUNG ]
