S3C4510B
SYSTEM MANAGER
4
SYSTEM MANAGER
OVERVIEW
The S3C4510B microcontroller's System Manager has the following functions.
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To arbitrate system bus access requests from several master blocks, based on fixed priorities.
To provide the required memory control signals for external memory accesses. For example, if a master
block such as the DMA controller or the CPU generates an address which corresponds to a DRAM bank, the
System Manager's DRAM controller generates the required normal/EDO or SDRAM access signals. The
interface signals for normal/EDO or SDRAM can be switched by SYSCFG[31].
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To provide the required signals for bus traffic between the S3C4510B and ROM/SRAM and the external I/O
banks.
To compensate for differences in bus width for data flowing between the external memory bus and the
internal data bus.
S3C4510B supports both little and big endian for external memory or I/O devices.
NOTE
By generating an external bus request, an external device can access the S3C4510B's external memory
interface pins. In addition, the S3C4510B can access slow external devices using a Wait signal. The Wait
signal, which is generated by the external device, extends the duration of the CPU's memory access
cycle beyond its programmable value.
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SAMSUNG [ SAMSUNG ]
