S3C4510B
INSTRUCTION SET
FORMAT 16: CONDITIONAL BRANCH
11
15
14
13
12
8
7
0
SOffset 8
1
1
0
1
Cond
[7:0] 8-bit Signed Immediate
[11:8] Condition
Figure 3-45. Format 16
OPERATION
The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition
codes. The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4
bytes) ahead of the current instruction.
The THUMB assembler syntax is shown in the following table.
Table 3-23. The Conditional Branch Instructions
Code
THUMB
ARM Equivalent
Action
Assembler
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
BEQ label
BNE label
BCS label
BCC label
BMI label
BPL label
BVS label
BVC label
BHI label
BLS label
BGE label
BEQ label
BNE label
BCS label
BCC label
BMI label
BPL label
BVS label
BVC label
BHI label
BLS label
BGE label
Branch if Z set (equal)
Branch if Z clear (not equal)
Branch if C set (unsigned higher or same)
Branch if C clear (unsigned lower)
Branch if N set (negative)
Branch if N clear (positive or zero)
Branch if V set (overflow)
Branch if V clear (no overflow)
Branch if C set and Z clear (unsigned higher)
Branch if C clear or Z set (unsigned lower or same)
Branch if N set and V set, or N clear and V clear
(greater or equal)
3-91
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