K9W4G08U1M
K9K2G08Q0M
K9K2G08U0M
K9W4G16U1M
K9K2G16Q0M
K9K2G16U0M
FLASH MEMORY
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/Ox
DIN final*
DIN 0
DIN 1
NOTES : DIN final means 2112(X8) or 1056(X16)
Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tCEA
CE
tCHZ*
tOH
tREH
tREA
tREA
tREA
RE
tRHZ*
tRHZ*
tOH
I/Ox
Dout
Dout
Dout
tRC
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
20