K9F5608U0A-YCB0,K9F5608U0A-YIB0
FLASH MEMORY
* Input Data Latch Cycle
tCLH
CLE
CE
tCH
tWC
tALS
ALE
tWP
tWP
tWP
WE
tWH
tDH
tDH
tDH
tDS
tDS
tDS
I/O0~7
DIN 1
DIN 511
DIN 0
* Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
CE
tREH
tCHZ*
tREA
tREA
tREA
RE
tRHZ*
tRHZ*
Dout
I/O0~7
R/B
Dout
Dout
tRR
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
15