K9F5608U0A-YCB0,K9F5608U0A-YIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE don’t-care
CE
WE
ALE
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
I/O0~7
CE
(Min. 10ns)
tCS
(Max. 45ns)
tCEA
tCH
CE
RE
tREA
tWP
WE
I/O0~7
out
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
Figure 4. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
CE
RE
ALE
tR
R/B
WE
Data Output(sequential)
00h
Start Add.(3Cycle)
I/O0~7
13
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