Preliminary
K5A3x80YT(B)C
MCP MEMORY
ORDERING INFORMATION
K 5 A 3 x 8 0 Y T C - T 7 5 5
Samsung
MCP Memory
SRAM Access Time
55 = 55 ns
Device Type
Dual Bank Boot Block NOR
+ fCMOS SRAM
Flash Access Time
7 = 70 ns
8 = 80 ns
NOR Flash Density
(Bank Size), (Organization)
32 : 32Mbit, (8Mb, 24Mb)
(x8/x16 Selectable)
Package
T = 69 TBGA
33 : 32Mbit, (16Mb, 16Mb)
(x8/x16 Selectable)
Version
C = 4th Generation
SRAM Density , Organization
8Mbit, x8/x16 Selectable
Block Architecture
T = Top Boot Block
B = Bottom Boot Block
Operating Voltage Range
2.7V to 3.3V
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VccF
Vss
Bank1
Address
Bank1
X
RESET
RD/BY
Cell Array
Dec
Latch &
Control
Y Dec
A0 to A18
(Common)
Bank1 Data-In/Out
Bank2 Data-In/Out
Y Dec
I/O
A-1,A19 to A20
BYTEF
Interface
Latch &
Control
&
X
Dec
Bank
Control
Bank2
Cell Array
Bank2
Address
CEF
Erase
OE
Control
High
Voltage
Gen.
WE
Program
Control
DQ0 to DQ7
DQ8 to DQ15
Clk gen.
Precharge circuit.
SA
UB
LB
SRAM
Main Cell Array
(512K x16, 1M x8)
Row
select
BYTES
CS1S
CS2S
Data
control
I/O Circuit
Control
logic
VccS
Vss
Column select
Bottom Boot Block
Revision 0.0
November 2002
- 3 -
SAMSUNG [ SAMSUNG ]
