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K4S641632H-UC75 参数 Datasheet PDF下载

K4S641632H-UC75图片预览
型号: K4S641632H-UC75
PDF下载: 下载PDF文件 查看货源
内容描述: 64MB H- SDRAM芯片规格54 TSOP- II与无铅(符合RoHS) [64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant)]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 14 页 / 146 K
品牌: SAMSUNG [ SAMSUNG ]
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SDRAM 64Mb H-die (x4, x8, x16)  
CMOS SDRAM  
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)  
Parameter  
AC input levels (Vih/Vil)  
Value  
2.4/0.4  
1.4  
Unit  
V
Input timing measurement reference level  
Input rise and fall time  
V
tr/tf = 1/1  
1.4  
ns  
V
Output timing measurement reference level  
Output load condition  
See Fig. 2  
3.3V  
Vtt = 1.4V  
1200Ω  
50Ω  
VOH (DC) = 2.4V, IOH = -2mA  
VOL (DC) = 0.4V, IOL = 2mA  
Output  
Output  
Z0 = 50Ω  
30pF  
30pF  
870Ω  
(Fig. 1) DC output load circuit  
(Fig. 2) AC output load circuit  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
60  
12  
18  
18  
42  
70  
75  
15  
20  
20  
45  
Row active to row active delay  
RAS to CAS delay  
tRRD(min)  
tRCD(min)  
tRP(min)  
14  
ns  
ns  
1
1
1
1
20  
Row precharge time  
20  
ns  
tRAS(min)  
tRAS(max)  
tRC(min)  
49  
ns  
Row active time  
100  
us  
Row cycle time  
60  
68  
65  
ns  
1
2,5  
5
Last data in to row precharge  
Last data in to Active delay  
Last data in to new col. address delay  
Last data in to burst stop  
tRDL(min)  
tDAL(min)  
tCDL(min)  
tBDL(min)  
tCCD(min)  
2
CLK  
-
2 CLK + tRP  
1
1
1
2
1
CLK  
CLK  
CLK  
2
2
Col. address to col. address delay  
3
CAS latency = 3  
CAS latency = 2  
Number of valid output data  
ea  
4
Notes :  
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time  
and then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change.  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.  
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.  
Rev. 1.3 August 2004