SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C for x4, x8)
Version
75
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
75
mA
mA
1
ICC2P CKE ≤ VIL(max), tCC = 10ns
1
1
Precharge standby current in
power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
15
6
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stable
ICC3P CKE ≤ VIL(max), tCC = 10ns
3
3
Active standby current in
power-down mode
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC3N
30
25
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks Activated
ICC4
115
mA
1
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
135
1
mA
mA
uA
2
3
4
C
L
Self refresh current
CKE ≤ 0.2V
400
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S6404(08)32H-TC**
4. K4S6404(08)32H-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.3 August 2004
SAMSUNG [ SAMSUNG ]
