K4H560838D
DDR SDRAM
AC Operating Test Conditions
(VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate (for imput only)
Input slew rate (I/O pins)
Value
Unit
V
Note
0.5 * VDDQ
1.5
V
0.5
V/ns
V/ns
V
0.5
VREF+0.31/VREF-0.31
VREF
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Load Circuit
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Delta Cap(max)
Unit
Input capacitance
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
1.5
3.5
0.5
pF
Input capacitance( CK, CK )
Data & DQS input/output capacitance
Input capacitance(DM)
CIN2
COUT
CIN3
1.5
3.5
3.5
3.5
5.5
5.5
0.25
0.5
pF
pF
pF
Rev. 2.2 Mar. ’03
- 20 -
SAMSUNG [ SAMSUNG ]
