DDR SDRAM 256Mb E-die (x4, x8)
DDR SDRAM
Ball Description (Bottom View)
64M x 4bit
1
2
3
VSSQ
NC
NC
NC
NC
VREF
VSS
DM
F
NC
VDDQ VSSQ VDDQ VSSQ
CK
CK
G
A12
CKE
H
A11
A9
A8
A7
K
A6
A4
VSS
M
VSS
A
DQ3
B
NC
C
DQ2
D
DQS
E
A5
L
J
7
8
9
VDD
NC
DQ0
NC
DQ1
NC
NC
WE
CAS
RAS
CS
BA1
A0
A2
A1
VDD
A3
VSSQ VDDQ VSSQ VDDQ VDD
BA0 A10/AP
VDDQ
NC
NC
NC
NC
NC
32M x 8bit
1
2
3
VSSQ
DQ7
VSS
A
NC
NC
NC
NC
VREF
VSS
DM
F
VDDQ VSSQ VDDQ VSSQ
CK
CK
G
A12
CKE
H
A11
A9
A8
A7
K
A6
A5
L
A4
VSS
M
DQ6
B
DQ5
C
DQ4
D
DQS
E
J
7
8
9
VDD
DQ0
VDDQ
DQ1
DQ2
DQ3
NC
NC
WE
CAS
RAS
CS
BA1
A0
A2
A1
VDD
A3
VSSQ VDDQ VSSQ VDDQ VDD
NC NC NC NC NC
BA0 A10/AP
Organization
64Mx4
Row Address
A0~A12
Column Address
A0-A9, A11
A0-A9
32Mx8
A0~A12
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.1 September. 2003
SAMSUNG [ SAMSUNG ]
