K4E171611D, K4E151611D
K4E171612D, K4E151612D
11. t
ASC
, t
CAH
are referenced to the earlier CAS falling edge.
CMOS DRAM
12. t
CP
is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
13. t
CWD
is referenced to the later CAS falling edge at word read-modify-write cycle.
14. t
CWL
is specified from W falling edge to the earlier CAS rising edge.
15. t
CSR
is referenced to the earlier CAS falling edge before RAS transition low.
16. t
CHR
is referenced to the later CAS rising edge after RAS transition low.
RAS
LCAS
UCAS
t
CSR
t
CHR
17.
t
DS,
t
DH
is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
18. t
ASC
≥6ns,
assume t
T
=2.0ns.
19. If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
20. If
t
RASS
≥100us,
then RAS precharge time must use
t
RPS
instead of
t
RP
.
21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
22. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
