BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
Pin Name
Pin Usage
External
Pin Layout Guide
VDDA1
VSSA1
VDDA2
VSSA2
VDDD
- Maintain the large width of lines as far as the pads.
- Place the port positions to minimize the length of power lines.
- Do not merge the analog powers with other power from other
blocks.
External
External
External
External
- Use good power and ground source on board.
VSSD
External
VDDO
External
VSSO
External
VBB
External
R_VIN
G_VIN
B_VIN
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
External/Internal
- Do not overlap with digital lines.
- Maintain the shortest path to pads.
ADCCLK
CDS1_CLK
CDS2_CLK
REFT
- Separate from all other analog signals
- Maintain the larger width and the shorter length as far as the pads.
- Separate from all other digital lines.
REFB
VCOM
BGR
IBIAS
- Test pins
ITEST
- SPEEDUP = set to "LOW"
STBY
SPEEDUP
STRTLN
EXT_MCTL
MCTL1,2
OEB
- Separated from the analog clean signals if possible.
- Do not exceed the length by 1,000um.
WRB
RDB
CSB
AD[2:0]
D[11:0]
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SAMSUNG [ SAMSUNG ]
