BL8531H
AFE FOR CCD/CIS SIGNAL PROCESSOR
BLOCK DIAGRAM
VDDA1 VSSA1
VDDA2
VSSA2
VDDD
VSSD
VBB
BGR REFT VCOM REFB
MCTL2
MCTL1
RED
R_VIN
CDS
PGA
EXT_MCTL
CLAMP
R_OFFSET[7:0]
R_GAIN[4:0]
R_CLAMP[3:0]; For only SHA mode
REF
GREEN
G_VIN
MUX
&
12
12
8
CDS
PGA
ADC
G1.5
CLAMP
D[11:0]
/MPU[7:0]
G_OFFSET[7:0]
G_GAIN[4:0]
G_CLAMP[3:0]; For only SHA mode
GAIN
MODE
BLUE
B_VIN
CDS
PGA
CLAMP
R_OFFSET[7:0]
B_GAIN[4:0]
CSB
Configuration
Register
B_OFFSET[7:0]
OEB
RDB
WRB
AD[2]
AD[1]
AD[0]
B_CLAMP[3:0]; For only SHA mode
R_OFFSET[7:0]
Input Offset
Register
(R,G,B)
8
MPU
PORT
G_OFFSET[7:0]
B_OFFSET[7:0]
R_CLAMP[3:0], R_GAIN[4:0]
G_CLAMP[3:0], G_GAIN[4:0]
B_CLAMP[3:0], B_GAIN[4:0]
Gain & Clamp
Level Register
(R,G,B)
CDS1_CLK
CDS2_CLK
STRTLN
ADCCLK
15
SAMSUNG [ SAMSUNG ]
