AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
CORE PIN DESCRIPTION
Name
VDD
VSS
I/O Type
DP
I/O Pad
vddd
vssd
Pin Description
Digital power supply
Digital ground
DG
VDDA
VSSA
VBB
FIN
FILTER
AP
AG
AB/DB
DI
AO
vdda
vssa
vbba
Analog power supply
Analog ground
Analog/Digital sub bias Power
PLL clock input
picc_bb
poar50_bb
- Pump out is connected to Filter
- A capacitor is connected between the pin and analog ground
20MHz~170MHz clock output
FOUT
PWRDN
DO
DI
pot12_bb
picc_bb
FSPLL clock power down.
- PWRDN is High, PLL do not operating under this condition.
- If isn't used this pin, tied to VSS.
P[5:0]
M[7:0]
S[1:0]
DI
DI
DI
picc_bb
picc_bb
picc_bb
The values for 6bit programmable pre-divider.
The values for 8bit programmable main divider.
The values for 2bit programmable post scaler.
I/O Type Abbr.
— AI: Analog Input
— DI: Digital Input
— AO: Analog Output
— DO: Digital Output
— AB: Analog Bidirectional
— DB: Digital Bidirectional
— AP: Analog Power
— DP: Digital Power
— AG: Analog Ground
— DG: Digital Ground
2
SAMSUNG [ SAMSUNG ]
