STU/D412S
S a mHop Microelectronics C orp.
Ver 1.0
N-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V
DSS
40V
FEATURES
Super high dense cell design for low R
DS(ON)
.
Rugged and reliable.
TO-252 and TO-251 Package.
I
D
22A
R
DS(ON)
(m
Ω
) Max
26
@
VGS=10V
40
@
VGS=4.5V
ESD Protected.
D
D
G
S
G
D
G
S
STU SERIES
TO-252AA(D-PAK)
STD SERIES
TO-251(l-PAK)
S
ABSOLUTE
Symbol
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J,
T
STG
MAXIMUM RATINGS (
T
C
=25
°
C unless otherwise noted
)
Parameter
Drain-Source Voltage
Gate-Source Voltage
T
A=
25 °C
a
Drain Current-Continuous
T
A=
70 °C
b
-Pulsed
Avalanche Energy
c
Limit
40
±20
22
17.5
80
10
25
16
-55 to 150
Units
V
V
A
A
A
mJ
W
W
°C
Maximum Power Dissipation
a
T
A=
25 °C
T
A=
70 °C
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R
JC
R
JA
Thermal Resistance, Junction-to-Case
a
Thermal Resistance, Junction-to-Ambient
a
5
50
°C/W
°C/W
Aug,07,2008
1
www.samhop.com.tw
SAMHOP [ SAMHOP MICROELECTRONICS CORP. ]
