Technical Note
BU2098F, BU2090F, BU2090FS
●Block diagram
BU2098F
Power-On Reset
SDA
SCL
L
a
t
c
h
Write
I2C BUS
Shift
Buffer
8bit
A0
Q0～Q7
Controller
Register
A1
A2
BU2090F/BU2090FS
L
a
t
c
h
Write
CLOCK
12bit
Controller
Shift
Buffer
Q0～Q11
Register
DATA
●Interfaces
BU2090F/BU2090FS
DATA, CLOCK
BU2090F/BU2090FS
BU2098F
Q0～Q11
Q0～Q7
VDD
VDD
OUT
OUT
IN
GND (VSS
)
GND (VSS)
GND (VSS
)
GND (VSS
)
BU2098F
BU2098F
SDA
BU2098F
SCL
A0～A2
VDD
VDD
VDD
VDD
VDD
IN
IN
IN
GND (VSS
)
GND (VSS
)
GND (VSS)
GND (VSS
)
GND (VSS)
GND (VSS
)
GND (VSS
)
GND (VSS)
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.06 - Rev.A
4/12
ROHM [ ROHM ]
