Datasheet
BR24G256-3
Block Diagram
A0
1
256Kbit EEPROM Array
8
VCC
8bit
Address
Decoder
Word
Data
15bit
A1
A2
2
3
4
7
6
5
WP
Address Register
Register
START
Control Circuit
STOP
SCL
SDA
ACK
High Voltage
Generating Circuit
Power Source
GND
Voltage Detection
Figure 3. Block Diagram
Pin Configuration
(TOP VIEW)
VCC
8
7
1
2
A0
WP
A1
A2
BR24G256-3
3
4
SCL
SDA
6
5
GND
Pin Descriptions
Terminal Input/
Descriptions
Name
Output
Input
Input
Input
-
Slave address setting
Slave address setting
Slave address setting
A0
A1
A2
Reference voltage of all input / output, 0V
Serial data input serial data output
GND
Input/
Output
SDA
Serial clock input
SCL
WP
Input
Input
-
Write protect terminal
Connect the power source.
VCC
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TSZ02201-0R2R0G100240-1-2
25.Feb.2013 Rev.002
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